Sam-Siewert-UAA-Small

Sam Siewert

Assistant Professor
Office: ENGR 227C
Phone: 907-786-6756
Email: ssiewert@uaa.alaska.edu

Biography

PATENTS AND INVENTIONS

2012 Invention Disclosure - A Method to Verify Video Encode, Transport, Decode and Display Latency Using Automatic Concurrent Pattern Generation and Recognition.

2009 US Filing 12/364,271 - Systems and Methods for Block-Level Management of Tiered Storage.

2009 US Filing 12/395,529 - Systems and Methods for Detection, Isolation, and Recovery of Faults.

2009 US Prov. Filing 61/233,579 - Scalable Virtualization Controller for Solid-State Storage (VxSSD).

2008 US Filing 12/395,509 - Storage System Front End - Transport Protocol Agnostic Driver design.

2008 US Pat. 7,370,326, granted May 6 - Prerequisite-based scheduler.

TEXTBOOK PUBLICATIONS

2006 S. Siewert, Real-time Embedded Components and Systems, Charles River Media / Thomson Delmar Learning, ISBN 1584504684.

JOURNAL PUBLICATIONS 

1)  S. Siewert, D. Nelson, “Solid State Drives in Storage and Embedded Applications”, Intel Technical Journal, July 2009. 

2)  G. Nutt, S. Brandt, A. Griff, and S. Siewert, "Dynamically Negotiated Resource Management for Virtual Environment Applications", IEEE Transactions on Knowledge and Data Engineering, MMIS'97 special section, August 1999.   

CONFERENCE PUBLICATIONS  

1)  S. Siewert, Greg Scott, “Next Generation Scalable and Efficient Data Protection”, Intel Developer’s Forum, San Francisco, California, September 2011.  

2)  S. Siewert, “Storage Acceleration, Driven by Autonomic Software”, Storage and Networking Industry Association, Storage Developer’s Conference, Santa Clara, California, September 2010. 

3)  S. Siewert, M. Vidalon, “Building a Continuing Education Program for Embedded Systems with Labs and Distance Support”, IACEE 11th World Conference on Continuing Engineering Ed., May 2008.  

4)  S. Siewert, Zach Pfeffer, “An Embedded Real-Time Autonomic Architecture”, IEEE Denver Technical Conference, April 2005. 

5)  S. Siewert, “IO Latency Hiding in Pipelined Architectures”, IEEE Denver Tech. Conf., April 2005.  

6)  Z. Pfeffer, S. Siewert, “A Machine to Support Autonomic Computing”, IEEE Denver Tech. Conf., April 2005. 

7)  S. Siewert, "Experiments with a Real-Time Multi-Pipeline Architecture for Shared Control", IEEE Aerospace Conference, Big Sky, Montana, March 2001. 

8)  S. Siewert and G. Nutt, "Multi-Epoch Scheduling within the Real-Time Execution Performance Agent Framework", IEEE Real-Time Systems Symposium, Orlando, Florida, November 2000.

9)  S. Siewert, G. Nutt, and E. Hansen, "The Real-Time Execution Performance Agent - An Approach for Balancing Hard and Soft Real-Time Execution for Space Applications ", Int’l Symposium on AI, Robotics, and Automation in Space, Noordwijk, Holland, June 1999.  

10) R. Shepperd, J. Willis, E. Hansen, J. Faber, S. Siewert, “DATA-CHASER: A Demonstration of Advanced Mission Operations Technologies”, IEEE Aerospace Conference, 1998. 

11) S. Siewert and E. Hansen, "Lowering the Cost of Mission Operations Through End-to-End Automation", Int’l Symposium on AI, Robotics, and Automation in Space, Tokyo, Japan, June 1997.  

12) S. Siewert, G. Nutt, and M. Humphrey, "Real-Time Parametrically Controlled In-Kernel Pipelines", Third IEEE Real-time Technology and Applications Symposium, Montreal, Canada, June 1997. 

13) G. Radideau, S. Chien, J. Willis, S. Siewert, P. Stone, “Interactive, Repair-Based Planning and Scheduling for Shuttle Payload Operations”, IEEE Aerospace Conference, Big Sky, Montana, 1997.

14) S. Siewert and Elaine Hansen, "A Distributed Operations Automation Testbed to Evaluate System Support for Autonomy and Operator Interaction Protocols", The ESA/DLR 4th International Symposium on Space Mission Operations and Ground Data Systems, Munich, Germany, Sept. 1996.  

15) S. Siewert and L. McClure, "A System Architecture to Advance Small Satellite Mission Operations Autonomy", 9th Annual AIAA/Utah State University Conference on Small Satellites, Logan, Utah, September 1995.    

R&D PUBLICATIONS 

1)  S. Siewert, “Revolutionary Methods to Handle Data Durability Challenges for Big Data”, Intel White Paper, September 2012. 

2)  S. Siewert, “Cloud-based Education, Part 3: Cloud-based robotics for education”, IBM developerWorks, February 2012. 

3)  S. Siewert, “Cloud-based education, Part 2: Tapping Cloud-based High Performance Computing for Education”, IBM developerWorks, January 2012. 

4)  S. Siewert, “Cloud-based education, Part 1: E-learning strategy for instructors”, IBM developerWorks, December 2011.  

5)  S. Siewert, “ Using Intel® VTune™ Performance Analyzer and Intel® Performance  Primitives  for Real-time Media Optimization”, Intel Corporation, June 2009. 

6)  S. Siewert, “Using SSE and IPP to Accelerate Image Processing Algorithms”, Intel Corporation, August 2009. 

7)  S. Siewert, “Infrastructure architecture essentials, Part 7: High-performance computing off the shelf”  , IBM developerWorks, December 2008. 

8)  S. Siewert, “Infrastructure architecture essentials, Part 5: Content delivery and distribution network design”  , IBM developerWorks, November 2008. 

9)  S. Siewert, “Infrastructure architecture essentials, Part 4: Scalable enterprise systems management”  , IBM developerWorks, October 2008.  

10) S. Siewert, “Infrastructure architecture essentials, Part 3: System design methods for scaling”, IBM developerWorks, October 2008.  

11) S. Siewert, “Infrastructure architecture essentials, Part 2: Find, avoid, and eliminate system bottlenecks”, IBM developerWorks, October 2008. 

12) S. Siewert, “Architecting a grid from components”, IBM developerWorks, September 2007.  

13) S. Siewert, “SoC drawer: The Cell Broadband Engine chip: High-speed offload for the masses”, IBM developerWorks, April 2007.

14) S. Siewert, “SoC drawer: Opportunities and challenges for SoC designs serving the digital content revolution”, IBM developerWorks, Jan 2007. 

15) S. Siewert, “SoC drawer: Eyes inside the silicon”, IBM developerWorks, October 2006. 

16) S. Siewert, “SoC drawer: SoC design for hardware acceleration, Part 2”, IBM developerWorks, August 2006.  

17) S. Siewert, “SoC drawer: SoC design for hardware acceleration, Part 1”, IBM developerWorks, June 2006.  

18) S. Siewert, “SoC drawer: SoC prognostication”, IBM developerWorks, May 2006.  

19) S. Siewert, “SoC drawer: Detecting and correcting I/O and memory errors”, IBM developerWorks, March 2006.  

20) S. Siewert, “SoC drawer: Shared resource management”, IBM developerWorks, February 2006.  

21) S. Siewert, “SoC drawer: Real-time resource management”, IBM developerWorks, January 2006.  

22) S. Siewert, “SoC drawer: SoC concurrent development”, IBM developerWorks, December 2005.  

23) S. Siewert, “SoC drawer: Function allocation and specification”, IBM developerWorks, Nov. 2005. 

24) S. Siewert, “SoC drawer: The resource view”, IBM developerWorks, October 2005.  

25) S. Siewert, “Big Iron Lessons, Part 6: The right coprocessor can help with encryption”, IBM developerWorks, August 2005.  

26) S. Siewert, “Big Iron Lessons, Part 5: Introduction to cryptography, from Egypt through Enigma”, IBM developerWorks, July 2005.  

27) S. Siewert, “Autonomic Architectures: Apply RAS architecture lessons to the autonomic self- CHOP roadmap”, IBM developerWorks, July, 2005.  

28) S. Siewert, “Big Iron Lessons, Part 4: Power, cooling, and performance: Find the right balance”, IBM developerWorks, May 2005.  

29) S. Siewert, “Big Iron Lessons, Part 3: Performance monitoring and tuning”, IBM developerWorks, April 2005.  

30) S. Siewert, “Big Iron Lessons, Part 2: Reliability and availability: What's the difference?”, IBM developerWorks, March 2005.  

31) S. Siewert, “Big Iron Lessons, Part 1: FPU architecture, now and then”, IBM developerWorks, February 2005.  

32) S. Siewert, “A real-time execution performance agent interface for confidence-based scheduling”, Ph.D. thesis, T 2000 .Si199, U. of Colorado library, 2000.  

33) S. Siewert, “A Common Core Language Design for Layered Language Extension”, M.S. thesis, T 1993 .Si19, U. of Colorado library, 1993.

Education

2000 PhD, Computer Science, University of Colorado, Boulder

1993 MS, Computer Science, University of Colorado, Boulder

1991 28 Credit Hours, Computer System Design Engineering, University of Houston, Clear Lake

1989 BS, Aerospace and Mechanical Engineering, University of Notre Dame

1985 7.5 Credit Hours, Early Admission, Physics/Philosophy, University of California, Berkeley